A microelectronic package containing one or more semiconductor die electrically interconnected with multiple discrete components is commonly referred to as a “System-in-Package” or “SiP.” The discrete components are typically Surface Mount Devices (SMDs), such as discrete resistors, capacitors, inductors, and diodes. The SiP can be produced as a Fan Out Wafer Level Package (FO-WLP). In one example of a FO-WLP packaging approach, semiconductor die are positioned on a temporary substrate in predetermined groupings with the SMDs. A panelization or overmolding process is then carried-out to encapsulate the die and SMDs in a molded panel. Redistribution Layers (RDLs) containing metal interconnect lines are produced over the frontside of the molded panel to provide the desired wiring structure between the die and the SMDs. A Ball Grid Array (BGA) or another contact array can then be produced over the RDLs and in electrical contact with the interconnect lines to provide externally-accessible points of contact to the microelectronic devices (e.g., semiconductor die and SMDs) embedded in the panel body. Additional processes can be performed, as desired, to impart the FO-WLPs with various other features, such as a backside contact array, heat sink, radio frequency (RF) shield, or the like. Lastly, the panel is singulated to yield a plurality of SiPs each including a molded package body containing at least one semiconductor die interconnected with at least one and typically multiple SMDs.
As SiP complexity increases, it is not uncommon for a single SiP to contain a relatively large number of discrete SMDs interconnected with one or more semiconductor die contained within a molded package body. For example, certain SiP Single Chip Modules (SCMs) are currently produced containing over one hundred discrete SMDs, which are positioned throughout the module and interconnected with a semiconductor die when the SiP is complete. When a molded panel FO-WLP fabrication process is utilized to produce the SiP, the SMDs and other microelectronic components (e.g., semiconductor die) can be placed on a temporary substrate utilizing a pick-and-place tool. Placement of the microelectronic components is typically carried-out sequentially on a one-by-one basis. If not placed with sufficient accuracy, the SMDs may be offset from their desired positions within the molded panel; and subsequently-produced interconnect lines may fail to contact the terminals of the misplaced SMDs during RDL build-up. Failure to establish electrical contact with one or more SMDs can result in rejection of the entire SiP upon testing. Pre-panelization placement of the SMDs is therefore carefully performed and can be a time consuming process. In the aggregate, SMD placement can take several minutes for SiPs containing a relatively large number of SMDs, and the better part of a day for molded panels containing relatively large numbers of SiPs produced in parallel.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.